location of object files in makefile

[daviddoria]

I have two directories, A and B. The makefile in B needs to compile some things from B into .o file (still in B), but also some things from A. The problem is, it creates the Astuff.o in A, and therefore when it continues and tries to link there are errors (because it can't find all the .o files).

Is there a way to specify "force build .o file here"?

Thanks!

Dave

[cable_txg]

Try using variables for your output files - it saves a lot of headache and searching. eg:

OBJ_FILES=/tmp/Object_Codes

Then link:
gcc -o $(OBJ_FILES)/myTest.o myTest.c

[daviddoria]

you'd have to use -c instead of -o right?

but otherwise thats a good idea

[nspmangalore]

no daviddoria,
it has to be -o, since thats the way you specify the path and name of the compiled file.
-c is required to compile the file into object files(these files may not be executable).

[daviddoria]

right, thats what i want - object files , not executables

can you specify the name and path with -c ? or use -c and -o together ?

[nspmangalore]

oh. in that case, use -c flag, followed by -o OUTPATH...

i.e.
gcc -c -o $(OBJ_FILES)/myTest.o myTest.c